From 4c2b7ffd2c0644b53d2fc4c2ce0487e7ce2c8a27 Mon Sep 17 00:00:00 2001 From: "djm@kirby.fc.hp.com" Date: Wed, 27 Jul 2005 12:07:07 -0700 Subject: [PATCH] Add xen-shared-info offset generation Signed-off-by: Eddie Dong Signed-off-by: Kevin Tien Signed-off-by: Fred Yang --- xen/arch/ia64/Makefile | 24 ++++++- xen/arch/ia64/asm-xsi-offsets.c | 114 ++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 2 deletions(-) create mode 100755 xen/arch/ia64/asm-xsi-offsets.c diff --git a/xen/arch/ia64/Makefile b/xen/arch/ia64/Makefile index 5e497818cc..5aa2a9fd96 100644 --- a/xen/arch/ia64/Makefile +++ b/xen/arch/ia64/Makefile @@ -34,9 +34,29 @@ default: $(OBJS) head.o ia64lib.o xen.lds.s > $(BASEDIR)/System.map -asm-offsets.s: asm-offsets.c $(BASEDIR)/include/asm-ia64/.offsets.h.stamp +asm-offsets.s: asm-offsets.c $(BASEDIR)/include/asm-ia64/.offsets.h.stamp asm-xsi-offsets.h $(CC) $(CFLAGS) -S -o $@ $< +asm-xsi-offsets.s: asm-xsi-offsets.c + $(CC) $(CFLAGS) -S -o $@ $< + +asm-xsi-offsets.h: asm-xsi-offsets.s + @(set -e; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was auto-generated from $<"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + echo "#ifndef __ASM_XSI_OFFSETS_H__"; \ + echo "#define __ASM_XSI_OFFSETS_H__"; \ + echo ""; \ + sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}"; \ + echo ""; \ + echo "#endif") <$< >$@ + mv $@ $(BASEDIR)/include/asm + $(BASEDIR)/include/asm-ia64/.offsets.h.stamp: # Need such symbol link to make linux headers available [ -e $(BASEDIR)/include/linux ] \ @@ -60,6 +80,7 @@ ia64lib.o: clean: rm -f *.o *~ core xen.lds.s $(BASEDIR)/include/asm-ia64/.offsets.h.stamp asm-offsets.s + rm -f asm-xsi-offsets.s rm -f lib/*.o # setup.o contains bits of compile.h so it must be blown away @@ -68,4 +89,3 @@ delete-unfresh-files: # rm -f setup.o .PHONY: default clean delete-unfresh-files - diff --git a/xen/arch/ia64/asm-xsi-offsets.c b/xen/arch/ia64/asm-xsi-offsets.c new file mode 100755 index 0000000000..4951d4fbae --- /dev/null +++ b/xen/arch/ia64/asm-xsi-offsets.c @@ -0,0 +1,114 @@ +/* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */ +/* + * asm-xsi-offsets.c_ + * Copyright (c) 2005, Intel Corporation. + * Kun Tian (Kevin Tian) + * Eddie Dong + * Fred Yang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ + +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed + * to extract and format the required data. + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_VTI +#include +#include +#endif // CONFIG_VTI + +#define task_struct vcpu + +#define DEFINE(sym, val) \ + asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + +#define BLANK() asm volatile("\n->" : : ) + +#define OFFSET(_sym, _str, _mem) \ + DEFINE(_sym, offsetof(_str, _mem)); + +#ifndef CONFIG_VTI +#define SHARED_ARCHINFO_ADDR SHAREDINFO_ADDR +#endif + +void foo(void) +{ + + DEFINE(XSI_BASE, SHARED_ARCHINFO_ADDR); + + DEFINE(XSI_PSR_I_OFS, offsetof(arch_vcpu_info_t, interrupt_delivery_enabled)); + DEFINE(XSI_PSR_I, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, interrupt_delivery_enabled))); + DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ipsr))); + DEFINE(XSI_IPSR_OFS, offsetof(arch_vcpu_info_t, ipsr)); + DEFINE(XSI_IIP_OFS, offsetof(arch_vcpu_info_t, iip)); + DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iip))); + DEFINE(XSI_IFS_OFS, offsetof(arch_vcpu_info_t, ifs)); + DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ifs))); + DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(arch_vcpu_info_t, precover_ifs)); + DEFINE(XSI_PRECOVER_IFS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, precover_ifs))); + DEFINE(XSI_ISR_OFS, offsetof(arch_vcpu_info_t, isr)); + DEFINE(XSI_ISR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, isr))); + DEFINE(XSI_IFA_OFS, offsetof(arch_vcpu_info_t, ifa)); + DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ifa))); + DEFINE(XSI_IIPA_OFS, offsetof(arch_vcpu_info_t, iipa)); + DEFINE(XSI_IIPA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iipa))); + DEFINE(XSI_IIM_OFS, offsetof(arch_vcpu_info_t, iim)); + DEFINE(XSI_IIM, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iim))); + DEFINE(XSI_TPR_OFS, offsetof(arch_vcpu_info_t, tpr)); + DEFINE(XSI_TPR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, tpr))); + DEFINE(XSI_IHA_OFS, offsetof(arch_vcpu_info_t, iha)); + DEFINE(XSI_IHA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iha))); + DEFINE(XSI_ITIR_OFS, offsetof(arch_vcpu_info_t, itir)); + DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, itir))); + DEFINE(XSI_ITV_OFS, offsetof(arch_vcpu_info_t, itv)); + DEFINE(XSI_ITV, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, itv))); + DEFINE(XSI_PTA_OFS, offsetof(arch_vcpu_info_t, pta)); + DEFINE(XSI_PTA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pta))); + DEFINE(XSI_PSR_IC_OFS, offsetof(arch_vcpu_info_t, interrupt_collection_enabled)); + DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, interrupt_collection_enabled))); + DEFINE(XSI_PEND_OFS, offsetof(arch_vcpu_info_t, pending_interruption)); + DEFINE(XSI_PEND, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pending_interruption))); + DEFINE(XSI_INCOMPL_REGFR_OFS, offsetof(arch_vcpu_info_t, incomplete_regframe)); + DEFINE(XSI_INCOMPL_REGFR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, incomplete_regframe))); + DEFINE(XSI_DELIV_MASK0_OFS, offsetof(arch_vcpu_info_t, delivery_mask[0])); + DEFINE(XSI_DELIV_MASK0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, delivery_mask[0]))); + DEFINE(XSI_METAPHYS_OFS, offsetof(arch_vcpu_info_t, metaphysical_mode)); + DEFINE(XSI_METAPHYS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, metaphysical_mode))); + + DEFINE(XSI_BANKNUM_OFS, offsetof(arch_vcpu_info_t, banknum)); + DEFINE(XSI_BANKNUM, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, banknum))); + + DEFINE(XSI_BANK0_R16_OFS, offsetof(arch_vcpu_info_t, bank0_regs[0])); + DEFINE(XSI_BANK0_R16, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, bank0_regs[0]))); + DEFINE(XSI_BANK1_R16_OFS, offsetof(arch_vcpu_info_t, bank1_regs[0])); + DEFINE(XSI_BANK1_R16, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, bank1_regs[0]))); + DEFINE(XSI_RR0_OFS, offsetof(arch_vcpu_info_t, rrs[0])); + DEFINE(XSI_RR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, rrs[0]))); + DEFINE(XSI_KR0_OFS, offsetof(arch_vcpu_info_t, krs[0])); + DEFINE(XSI_KR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, krs[0]))); + DEFINE(XSI_PKR0_OFS, offsetof(arch_vcpu_info_t, pkrs[0])); + DEFINE(XSI_PKR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pkrs[0]))); + DEFINE(XSI_TMP0_OFS, offsetof(arch_vcpu_info_t, tmp[0])); + DEFINE(XSI_TMP0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, tmp[0]))); + +} -- 2.30.2